JEDEC JESD22-B109C 倒装芯片拉脱试验

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JEDEC

STANDARD

Flip Chip Tensile Pull

JESD22-B109C

(Revision of JESD22-B109B, July 2014)

MARCH 2021

JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

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标签： #JEDEC

摘要：

本页面详细介绍JEDEC JESD22-B109C标准规范，该标准专用于倒装芯片（Flip Chip）封装中焊点与基板界面强度的拉脱试验（Pull Test）。文档涵盖试验目的、样品制备条件、测试设备要求、拉脱速率设定以及失效判据，旨在为半导体封装、电子组装及可靠性测试工程师提供精确的操作指南。通过本页可获取完整的试验流程、数据解读方法及常见失效模式分析，确保倒装芯片在先进封装工艺下的机械可靠性验证合规。适合从事SMT、微电子封装及质量控制的专业人士参考。

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