JEDEC JESD22-B118A 半导体晶圆以及芯片背面外目检

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JEDEC

STANDARD

Semiconductor Wafer and Die

Backside External Visual Inspection

JESD22-B118A

Revision of JESD22-B118, March 2011, Reaffirmed, June 2016

NOVEMBER 2021

JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

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标签： #导体 #JEDEC

摘要：

本文档详细介绍了 JEDEC 标准 JESD22-B118A 中关于半导体晶圆以及芯片背面外观检查（外目检）的规范与要求。该标准为半导体封装与测试环节提供了关键的质量控制依据，明确规定了晶圆背面与芯片背面的可接受缺陷类型、检验条件、判定标准以及抽样方法。通过遵循该标准，制造商能够有效识别背面划痕、污染、裂纹、金属残留等潜在工艺异常，从而提升产品的可靠性、降低封装过程中的失效风险。对于从事半导体制造、封装、质量保证以及失效分析的工程师而言，掌握 JESD22-B118A 的检视要点是确保晶圆级与芯

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